1. Field of the Invention
The present invention relates to power amplifiers, and specifically to a power amplifier circuit including a feedforward error path coupled to an output of at least one of a plurality of combined power amplifiers for canceling the distortion signal component from a carrier signal output from the plurality of combined amplifiers.
2. Description of Related Art
Wireless infrastructure equipment providers design high power linear amplifier circuits to amplify envelope modulated signals in, for example, wireless communications base stations. In such a design, a feedforward amplifier circuit can be employed to compensate for distortion added to a carrier signal as a result of its amplification. In such a circuit, an input modulated signal will be split into two signal pathsxe2x80x94a main output path and an error path. The signal component coupled onto the main output path is amplified and then delayed before it is output from the amplifier circuit. The signal component on the error path is delayed by a predetermined amount to cancel the carrier signal component from a portion of the amplified main path signal component that is coupled to the error path. The remaining distortion signal component is then amplified and delayed by a predetermined amount before being recombined with the amplified signal component to compensate for the distortion therein due to, for example, nonlinear transconductance (if a FET device is used as the amplifier), junction capacitance and the saturation effects of the amplifier that result in signal clipping.
In conventional feedforward amplifier circuit designs, it is desirable to delay match the main output path signal with the error path signal by placing an error transmission delay (ETD) block between the output of the main amplifier and the amplified signal output coupler to the error path. Because this ETD block is designed to match the error path propagation delay, and because of the low losses, small size and requisite delays necessary for such error matching, the ETD block is typically implemented with a filter having several high Q poles of selectivity, where Q represents the quality factor of the resonators used to realize the filter.
Microstrip lines have been used in the past for the delay element in both the main path and the error path. However, for a feedforward linear power amplifier (LPA) circuit operating at frequencies greater than 800 MHz, the transmission loss associated with microstrip lines is too high for cost effective implementation. In addition, as quarter-wavelength microstrip lines may be used to create resonators having Qs in the hundreds, it is impractical to use such devices to implement a filter with a Q in the tens of thousands as is necessary with the above-discussed feedforward amplifier circuit.
One practical way to implement such a high Q filter is to use quarter-wavelength coaxial resonators made from silver-plated machined metal blocks. However, even with this type of filter, several resonators are required to create a filter with a high enough Q to generate a requisite main path delay that in typical applications is approximately 10 ns.